Kenneth Edward Batcher

Kenneth Edward Batcher (December 27, 1935 – August 22, 2019) was an American academic who was emeritus professor of Computer Science at Kent State University. He also worked as a computer architect at Goodyear Aerospace in Akron, Ohio for 28 years.

Background Kenneth Edward Batcher was born on December 27, 1935 in Queens, New York, to Lois and Ralph Batcher. His parents met at Iowa State University and later relocated to New York City after graduation. His father, Ralph R. Batcher, was the Chief Engineer of The A. H. Grebe Radio Company until its bankruptcy in 1932.

Batcher graduated from Brooklyn Technical High School,

Career and achievements Among the designs he worked on at Goodyear were the:

Massively Parallel Processor (16,384 custom bit-serial processors {8 to a chip} organized in a SIMD 128 x 128 processor array with additional CPU rows for fault-tolerance) which was located at the NASA Goddard Space Flight Center, and is now in the Smithsonian. This unit predates Danny Hillis' Thinking Machines Corporation's Connection Machine The Goodyear STARAN associative processor arrays, a version of which (called ASPRO) was found in the US Navy Northrop Grumman E-2 Hawkeye radar planes.

Batcher published several technical papers and owns 14 patents of his own. "He discovered two parallel sorting algorithms: the odd-even mergesort and the bitonic mergesort". He is also a discoverer of scrambling data method in a random access memory which allows accesses along multiple dimensions. These memories were used in the STARAN and the MPP parallel processors.

Awards In 1980, he received an Arnstein Award presented by Goodyear Aerospace Corporation for technical achievement.

Batcher is known for his half-serious, half-humorous definition that "A supercomputer is a device for turning compute-bound problems into I/O-bound problems."

Publications Sorting Networks and their Applications, 1968 Spring Joint Computer Conference, AFIPS Proc. vol. 32, pp 307–314. As author or co-author in "Journal articles" On the Number of Stable States in a NOR Network, IEEE Trans. on Computers, vol. EC-14, no. 6, pp 931–932, Dec. 1965. The Multi-Dimensional Access Memory in STARAN, IEEE Trans. on Computers, vol. C-26, no. 2, pp 174–177, Feb. 1977. Design of a Massively Parallel Processor, IEEE Trans. on Computers, vol. C-29, no. 9, pp 836–840, Sept. 1980. Bit-Serial Parallel Processing Systems, IEEE Trans. on Computers, vol. C-31, no. 5, pp 377–384, May 1982. Adding Multiple-Fault Tolerance to Generalized Cube Networks, IEEE Trans. on Parallel and Distributed Systems vol. 5, no. 8, pp 785–792, Aug. 1994 (co-authored with C. J. Shih). A Multiway Merge Sorting Network, IEEE Trans. on Parallel and Distributed Systems, vol. 6, no. 2, pp 211–215, Feb. 1995 (co-authored with De-Lei Lee). Minimizing Communication in the Bitonic Sort, IEEE Trans. on Parallel and Distributed Systems, vol. 11, no. 5, pp 459–474, May 2000 (co-authored with Jae-Dong Lee).

Book chapters authored by Kenneth E. Batcher The STARAN Computer, Infotech State of the Art Report on Supercomputers, vol. 2, pp 33–49, 1979. MPP: A High-Speed Image Processor, Algorithmically Specialized Parallel Computers, edited by Snyder, Jamieson, Gannon, and Siegel, Academic Press, 1985, pp 59–68. The Massively Parallel Processor System Overview, The Massively Parallel Processor, edited by J. L. Potter, The MIT Press, 1985, pp 142–149. Array Unit, The Massively Parallel Processor edited by J. L. Potter, The MIT Press, 1985, pp 150–169. Array Control Unit, The Massively Parallel Processor edited by J. L. Potter, The MIT Press, 1985, pp 170–190. Staging Memory, The Massively Parallel Processor edited by J. L. Potter, The MIT Press, 1985, pp 191–204. MPP System Software, The Massively Parallel Processor edited by J. L. Potter, The MIT Press, 1985, pp 261–275. Retrospective: Architecture of a Massively Parallel Processor, 25 Years of the Int'l. Symposia on Computer Architecture - Selected Papers, edited by Gurindar Sohi, ACM Press, 1998, pp 15–16.

U.S. patents with Kenneth E. Batcher as the inventor or one of the inventors The patent number is followed by the title and the year issued.

3,183,363 Logic Mechanization System, 1965 (multiple inventors) 3,300,762 Multiple Response Resolver Apparatus, 1967 3,418,632 Means for Merging Sequences of Data, 1968 3,428,946 Means for Merging Data 1969 3,605,024 Apparatus for Shifting Data in a Long Register, 1971 3,681,781 Storing and Retrieval Method, 1972 3,711,692 Determination of Number of Ones in a Data Field by Addition, 1973 3,786,448 Multiple Access Plated Wire Memory, 1974 (multiple inventors) 3,800,289 Multi-Dimensional Access Solid State Memory, 1974 3,812,467 Permutation Network, 1974 3,936,806 Solid State Associative Processor Organization, 1976 4,314,349 Processing Element for Parallel Array Processors, 1982 4,727,474 Staging Memory for Massively Parallel Processor, 1988 5,153,843 Layout of Large Multistage Interconnection Networks, 1992