Srimanta Baishya

Srimanta Baishya is an Indian academician and Professor at the National Institute of Technology Silchar in the Department of Electronics and Communications Engineering. He earned his B.E. in electrical engineering from Assam Engineering College in Guwahati, followed by an M.Tech. in electrical engineering from the Indian Institute of Technology Kanpur. Baishya further pursued his Ph.D. in MOS Modeling from Jadavpur University in Kolkata. Presently, he serves as a professor at NIT Silchar, focusing on research areas such as MOS physics, modeling, and MEMS.

Career In his tenure at NIT Silchar, he has held prominent administrative positions, including the Dean of Academics, Dean of Research & Consultancy, and the Head of the department.

Selected bibliography Selected articles S. Baishya, A. Mallik, and C. K. Sarkar, “A Threshold Voltage Model for Short-Channel MOSFETs Taking into Account the Varying Depth of Channel Depletion Layers Around the Source and Drain,” Microelectronics Reliability, pp. 17 – 22, vol. 48, January 2008. S. Baishya, A. Mallik, and C. K. Sarkar, “A Pseudo-two-dimensional Subthreshold Surface Potential Model for Dual-material Gate MOSFETs,” IEEE Transactions on Electron Devices, pp. 2520–2525, vol. 54, September 2007. S. Baishya, A. Mallik, and C. K. Sarkar, “A Surface Potential Based Subthreshold Drain Current Model for Short-channel MOS Transistors,” Semiconductor Science & Technology, pp. 1066–1069, vol. 22, 2007. S. Baishya, A. Mallik, and C. K. Sarkar, “Subthreshold Surface Potential and Drain Current Models for Short-channel Pocket-implanted MOSFETs,” Microelectronic Engineering, vol. 84, pp. 653–662, April 2007. S. Baishya, A. Mallik, and C. K. Sarkar, “A Subthreshold Surface Potential Model for Short-channel MOSFET Taking into Account the Varying Depth of Channel Depletion Layer due to Source and Drain Junctions,” IEEE Transactions on Electron Devices, vol. 53, pp. 507–514, March 2006.