Norman Jouppi

Norman Paul Jouppi is an American electrical engineer and computer scientist. He is currently VP, Engineering Fellow at Google.

Career Jouppi was one of the computer architects at the MIPS Stanford University Project (under John L. Hennessy), an early RISC project. He received his master's degree in electrical engineering from Northwestern University in 1980 and was awarded a PhD in 1984 from Stanford University. In 1984 he joined Digital Equipment Corporation's Western Research Laboratory. He worked at Compaq and at Hewlett-Packard in 2002, where he ran the Advanced Architecture Lab at HP Labs in Palo Alto from 2006 to 2008 and then the Exascale Computing Lab from 2008 to 2010 and the Intelligent Infrastructure Lab from 2010 to 2011. After that, he became a computer engineer at Google. He has been the tech lead for Google’s Tensor Processing Units (TPUs) since their inception in 2013.

He pioneered developments in the field of memory hierarchies (victim buffers, prefetching stream buffers multi-level exclusive caching), heterogeneous architectures (single ISA heterogeneous architectures) and the introduction of the CACTI simulator for memory design (modeling of cache time, area and power).

He was the principal architect of four microprocessors and contributed to the development of graphics accelerators. He also deals with telepresence technology and the application of nanophotonics in the computer field.

In 2015, he received the Eckert–Mauchly Award for contributions to the design and analysis of high performance processors and computer storage systems. In 2002 he became Hewlett Packard Fellow, in 2003 fellow of the IEEE for contributions to the design of high-performance processors and memory systems, and in 2007 fellow of the Association for Computing Machinery. The ACM awarded Jouppi its Alan D. Berenbaum Distinguished Service Award in 2013. In 2014 he received the Harry H. Goode Memorial Award. Also in 2014, he was elected a member of the National Academy of Engineering for contributions to the design of computer memory hierarchies. In 2019 he was named a Fellow of the AAAS, and in 2024 he received the IEEE Seymour Cray Computer Engineering Award.

From 2007 to 2011, he headed the ACM's computer architecture special interest group, SIGARCH.

From 1984 to 1996, he was also a consulting assistant or associate professor at Stanford University. He holds over 100 US patents. He previously served as a member of the editorial boards of Communications of the ACM and IEEE Computer Architecture Letters.