Keshab K. Parhi

Keshab K. Parhi (born 1959 in Bhadrak District, Odisha, India) is an electrical engineer and computer scientist. He is currently the Erwin A. Kelen Chair in the department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. His research addresses architecture design of VLSI integrated circuit chips for signal processing, communications, artificial intelligence, and cryptosystems with a focus on reducing latency and increasing speed, while also reducing chip area and energy consumption. His research has also addressed neural engineering and DNA computing.

Career

Parhi received the B. Tech. degree from the Indian Institute of Technology, Kharagpur in 1982, the M.S. degree from the University of Pennsylvania in 1984, and the Ph.D. degree from the University of California, Berkeley in 1988. He joined the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities in October 1988. He was promoted to associate professor with tenure in July 1992 and promoted to full professor in July 1995. From July 1997 to June 2022, he held the Edgar F. Johnson Professorship in Electronic Communication. Since July 2022, he holds the Erwin A. Kelen Chair in Electrical Engineering. From July 2008 to August 2011, he served as the director of graduate studies of the Electrical Engineering Program. Broadcom Corporation (2000-2002), and Medtronic (2006-2007). From 2005 to 2012, he served as founder, president, and chief scientist of Leanics Corp. Leanics was supported by SBIR funding from the National Science Foundation and the Department of Defense.

Research Parhi’s interdisciplinary research in late 1980s advanced the field of VLSI signal processing by integrating concepts from computer architecture, digital signal processing (DSP), and VLSI design. In particular, he developed algorithm transformations techniques such as unfolding and folding for DSP programs described by iterative data-flow graphs.

His research has led to pipelined-parallel architectures for signal processing operations such as recursive and adaptive digital filters, decision-feedback equalizers, Tomlinson-Harashima precoders, parallel decision-feedback decoders, and fast Fourier transforms. He has developed architectures for modern error correction encoders/decoders including turbo codes, low-density parity-check codes, and polar codes. These technologies are found in numerous integrated circuit chips for physical-layer communications in wired and wireless media that form the backbone of the internet.

His research has led to high-speed architectures for cryptosystems such as the advanced encryption standard (AES), post-quantum cryptography, and homomorphic encryption. He has also developed approaches to obfuscating integrated circuits using keys to prevent the sale of excess parts and to protect key parameters of the design. In the 1990s, Parhi worked on a DARPA funded project on high-level synthesis that led to the development of the Minnesota Architecture Synthesis System (MARS) for time-constrained and resource-constrained synthesis of data-flow graphs. His research group also developed the Hierarchical Energy Analysis Tool (HEAT) to estimate power consumption with circuit-simulation-level accuracy from logic-level simulation.

Literary works

Parhi has also authored over 725 papers and is inventor or co-inventor of 36 issued US patents.

Professional service

Parhi has served the Institute of Electrical and Electronics Engineers (IEEE) in various capacities. He has served as associate editor for numerous transactions published by the IEEE Circuits and Systems Society and the IEEE Signal Processing Society. His leadership roles include:

2022 – Fellow, American Institute for Medical and Biological Engineering for outstanding contributions to machine learning approaches for neuropsychiatric and ophthalmic disorders, and to synthesis of molecular computing systems

2021 – IEEE Circuits and Systems Society John Choma Education Award for contributions to VLSI signal processing education

2020 – Fellow, Association for Computing Machinery (ACM) for contributions to architectures and design tools for signal processing and networking accelerators

2020 – Fellow, National Academy of Inventors

2017 – Fellow, American Association for the Advancement of Science

2017 – IEEE Circuits and Systems Society Mac Van Valkenburg Award for pioneering contributions to VLSI digital signal processing architectures, design methodologies, and their applications to wired and wireless communications, and service to IEEE Circuits and Systems Society

2013 – Indian Institute of Technology, Kharagpur Distinguished Alumnus Award

2013 – Award for Outstanding Contributions to Post Baccalaureate, Graduate and Professional Teaching, University of Minnesota, Twin Cities

2012 – IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award for contributions to VLSI architectures and design methodologies for digital signal processing and communications circuits and systems.

2004 – Frederick Emmons Terman Award from the American Society of Engineering Education for authoring the textbook “VLSI Digital Signal Processing Systems: Design and Implementation” (Wiley, 1999)

2003 – IEEE Kiyo Tomiyasu Award for pioneering contributions to high-speed and low-power digital signal processing architectures for broadband communications systems

2001 – IEEE W.R.G. Baker Award

1999 – IEEE Circuits and Systems Society Golden Jubilee Medal

1994 – IEEE Circuits and Systems Society Darlington Best Paper Award

1991 – IEEE Browder J. Thompson Memorial Prize Paper Award

1991 – IEEE Signal Processing Society Young Author Award

1987 – Eli Jury Award for Excellence in Systems Research, University of California, Berkeley

1987 – Demetri Angelakos Award for altruistic activities afforded fellow graduate students, University of California, Berkeley