Giovanni De Micheli

Giovanni De Micheli is a research scientist in electronics and computer science. He is credited for the invention of the Network on a Chip design automation paradigm and for the creation of algorithms and design tools for electronic design automation (EDA). He is Professor and Director of the Integrated Systems laboratory at École Polytechnique Fédérale de Lausanne (EPFL), Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He was Director of the Electrical Engineering Institute at EPFL from 2008 to 2019 and program leader of the Swiss Federal Nano-Tera.ch program. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California, Berkeley, 1980 and 1983) under Alberto Sangiovanni-Vincentelli.

De Micheli is a Fellow of ACM, AAAS and IEEE; a Member of the Academia Europaea , of the European Academy of Engineering and an International Honorary Member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of Synthesis and Optimization of Digital Circuits (McGraw-Hill, 1994) and co-author and/or co-editor of ten other books and of over 950 publications. His citation h-index is above 100 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B) and STMicroelectronics. He has chaired several conferences, including DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989). the 2016 EDAA Lifetime Achievement Award; the 2016 IEEE/CS Harry H. Goode Memorial Award for seminal contributions to design and design tools of Networks on Chips; the 2012 IEEE/CAS Mac Van Valkenburg Award for contributions to theory, practice and experimentation in design methods and tools and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems.

His PhD students include Luca Benini, Rajesh K. Gupta, Jerry Yang, Vincent Mooney, Sungroh Yoon, E.Y. Chung, S. Murali, Irene Taurino, Francesca Puppo, Luca Amaru and Tajana Rosing.

Selected publications

L. Benini and G. De Micheli, Giovanni. "Networks on chips: A new SoC paradigm." Computer 35.1 (2002): 70–78. G. De Micheli. Synthesis and optimization of digital circuits McGraw Hill, 1994. L. Benini and G. De Micheli. Dynamic power management: design techniques and CAD tools. Springer Science & Business Media, 1997. R. Gupta, and G. De Micheli. "Hardware-Software Co-Synthesis for Digital Systems", IEEE Design and Test of Computers 10 (3), 29-41. S. Murali and G. De Micheli. "Bandwidth-constrained mapping of cores onto NoC architectures." Proceedings Design Automation and Test in Europe conference and exhibition. Vol. 2. IEEE, 2004. D. Bertozzi, A.Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and G. De Micheli. "NoC synthesis flow for customized domain specific multiprocessor systems-on-chip." IEEE Transactions on parallel and distributed systems 16, no. 2 (2005): 113–129. L. Benini and G. De Micheli. "System-level power optimization: techniques and tools." ACM Transactions on Design Automation of Electronic Systems (TODAES) 5.2 (2000): 115–192. L. Benini, A. Bogliolo, G. Paleologo, and G. De Micheli. "Policy optimization for dynamic power management" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18, no. 6, (1999): 813-833. A. Garg, A. Di Cara, I. Xenarios, L. Mendoza, and G. De Micheli. "Synchronous versus asynchronous modeling of gene regulatory networks", Bioinformatics, 24 no. 17, (2008) 1917-1925. M. De Marchi, D. Sacchetto, S. Frache, J. Zhang, P.E. Gaillardon, Y. Leblebici, and G. De Micheli, "Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs", IEDM, (2012) S. Bobba, A. Chakraborty, O. Thomas, P. Batude, T. Ernst, O. Faynot, D. Pan, and De Micheli, "CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits", ASPDAC (2011). L. Amaru, P.E. Gaillardon, and G. De Micheli, "Majority-inverter graph: A new paradigm for logic optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35, no. 5, (2015): 806-819.